Why This Field Matters

On June 25, 2026, IBM unveiled the world’s first sub-1-nanometer chip technology: a 0.7nm (7-angstrom) node that packs nearly 100 billion transistors onto a fingernail-sized chip, roughly twice the density of the 2nm chip it showed in 2021. The key is that it does not shrink transistors further but stacks them in 3D, an architecture IBM calls nanostack. The company claims up to 50% more performance or up to 70% better energy efficiency over 2nm, with a path to production in as early as five years. This is not a chip you can buy soon; it is a demonstration that the road past the supposed end of Moore’s Law is still open.

What deserves attention is that chips like this can no longer be drawn by hand. Placing and routing 100 billion transistors, and verifying leakage current and thermals one by one below 1nm, is impossible without EDA, electronic design automation, software. The finer the node, the larger the share carried by automation tooling. Verification alone already eats 60 to 70 percent of chip design effort, and that verification increasingly rests on code and automation algorithms. When analysts estimate the industry will need over a million additional workers by 2030, part of what they are describing is the parallel surge in demand for software and EDA engineers who work silicon through code, not just the process engineers touching the wafer.

Required Skills

This work does not reach its target with the language of hardware or software alone. Start with the fundamentals of digital circuits and computer architecture: describing RTL in Verilog, VHDL, or SystemVerilog, and reading where synthesis and timing break. In Silicon Valley this lives at FAANG-scale custom-silicon teams, at EDA vendors, and at fabless and accelerator startups. Plenty of engineers cross in from backend work, and the fastest route to value when they do is verification and automation.

Verification engineers are the scarcest right now: people who write testbenches in SystemVerilog and UVM, close coverage, and pair that with AI-based bug-prediction tools. On top of that sits the ability to go beyond merely using EDA tools and automate the whole design flow through scripting, stitching synthesis, place-and-route, and verification pipelines together in Python and Tcl, then parsing the tens of gigabytes of logs the tools emit to find bottlenecks. As AI-driven EDA arrives, hands that apply machine learning to placement optimization or regression-test selection grow more valuable still. Going deep on one axis is not enough; the engineer who holds both an eye for the circuit and the code that automates it stands at the center of this seat.

Career Path

Juniors usually start on a single slice of verification or one stage of an EDA flow. They write a testbench for a specific module and close its coverage, or tune synthesis and timing scripts while learning how the tool chain actually flows. The point of this stage is to learn by hand how a chip is verified on top of code and where a design breaks. Verification teams at foundries and fabless firms, EDA vendors like Synopsys, Cadence, and Siemens, and accelerator startups are the main starting lines.

Moving to senior, weight shifts from one module to designing verification methodology and automation infrastructure as a whole. You set the verification strategy for a new chip, build the regression environment, and decide how AI tooling fits into the flow. Higher still is the EDA and methodology architect, who decides early in the design cycle which tools and flows the next-generation node will need and translates constraints between the silicon team and the software team. As IBM’s 0.7nm showed, a chip below 1nm cannot be drawn without automation tooling underneath it. The smaller the node, the more the hands that build and wield that tooling are worth. Now that semiconductors and software are bound into one flow rather than split apart, the engineer who bridges the two is the first one needed.